Wireless communication devices such as handsets typically include low power frequency synthesizers that monitor a plurality of frequency channels to determine whether any transmissions are present on those channels. If a transmission is found to be present on a particular channel, the synthesizer tunes to the frequency of that channel to permit the user to receive the incoming transmission. Since the frequency synthesizer is usually the first circuit in the communications device that is actuated, and since it is actuated at frequent intervals (as often as once per millisecond) to continually monitor for incoming transmissions, optimization of its performance and minimization of the current consumed is desirable.
There have been several approaches to improving the performance of synthesizers. The "technology improvement" approach is concerned primarily with developing devices that have a lower output capacitance and/or a lower substrate capacitance. Lower capacitances permit the device to switch faster. In particular, emitter-coupled logic (ECL) utilizes this approach to achieve significantly faster operational speeds. ECL has a significant drawback, however, in that current is continually consumed, even when devices employing this technology are not switching (changing the states of the inputs and outputs).
Another approach is reduction of current consumption through improvement of circuit topology. That is, the amount of current consumed can be reduced if the size of the circuit and/or the number of circuit components can be reduced. Synthesizers typically include a prescaler circuit, which divides the input frequency by a desired factor. As the prescaler is one of the most current-hungry components in the synthesizer, this is where optimization and current consumption reduction efforts have been focused.